If high-speed PCB design can be as simple as connecting schematic nodes and as beautiful as you can see on a computer monitor, it will be a wonderful thing. However, unless designers are new to PCB design, or are extremely lucky, actual PCB design is usually not as easy as the circuit design they are engaged in. Before the design can finally work normally and someone confirms the performance, PCB designers are faced with many new challenges. This is the current status of high-speed PCB design-design rules and design guidelines continue to evolve. If you are lucky, they will form a successful solution.

The vast majority of PCBs are schematic designers who are proficient in the working principle and mutual influence of PCB components and various data transmission standards that constitute the input and output of the circuit board. The result of mutual cooperation between professional layout designers of what will happen after conversion to printed circuit copper wire. Usually, it is the schematic designer who is responsible for the success or failure of the final circuit board. However, the more a schematic designer knows about excellent layout techniques, the more opportunities there are to avoid major problems.

　If the design contains high-density FPGAs, there are likely to be many challenges placed in front of the well-designed schematic. Including hundreds of input and output ports, operating frequencies over 500MHz (which may be higher in some designs), and solder ball pitches as small as half a millimeter, all of which will lead to undesirable occurrences between design units Mutual influence.

Concurrent switching noise

　The first challenge is probably the so-called concurrent switching noise (SSN) or concurrent switching output (SSO). A large number of high-frequency data streams will cause problems such as ringing and crosstalk on the data line, and problems with ground bounce and power supply noise that affect the performance of the entire circuit board will also occur on the power supply and ground plane.

　In order to solve the ringing and crosstalk on high-speed data lines, switching to differential signals is a good first step. Since one line on the differential pair is a sink (Sink), and the other provides a source current, the inductive effect can be fundamentally eliminated. When using differential pairs to transmit data, because the current is kept local, it helps to reduce the "bounce" noise generated by the induced current in the return path. For radio frequencies up to hundreds of MHz or even several GHz, signal theory shows that the maximum signal power can be transmitted when impedance is matched. When the transmission line is not properly matched, reflections will occur. Only part of the signal will be transmitted from the sender to the receiving device, while other parts will bounce back and forth between the sender and the receiver. The quality of the differential signal implementation on the PCB will have a great effect on impedance matching (and other aspects).

The characteristic impedance of 100Ω has become the industry standard value for differential cables. The 100Ω differential line can be made with two 50Ω single-ended lines of equal length. Since the two traces are close to each other, the field coupling between the wires will reduce the differential mode impedance of the wires. In order to maintain an impedance of 100Ω, the width of the trace must be reduced a bit. As a result, the common mode impedance of each wire in a 100Ω differential pair will be slightly higher than 50 ohms.

　Theoretically, the size of the trace and the material used determine the impedance, but vias, connectors, and even device pads will introduce impedance discontinuities in the signal path. It is usually impossible not to use these things. Sometimes, in order to make more reasonable layout and wiring, it is necessary to increase the number of layers of the PCB, or add functions such as buried vias. Buried vias only connect part of the PCB layer, but while solving the transmission line problem, it also increases the production cost of the board. But sometimes there is no choice at all. As the signal speed gets faster and the space gets smaller and smaller, additional requirements such as buried vias begin to increase, which should become the cost factor of PCB solutions.

When using stripline wiring, the signal is sandwiched by FR-4 material. In the case of a microstrip line, a conductor is exposed in the air. Because air has the lowest dielectric constant (Er=1), the top layer is most suitable for laying some key signals, such as clock signals or high-frequency SERial-DESerial (SERDES) signals. The microstrip wiring should be coupled to the ground plane below, which reduces electromagnetic interference (EMI) by absorbing part of the electromagnetic field lines. In the stripline, all the electromagnetic field lines are coupled to the upper and lower reference planes, which greatly reduces EMI. If possible, you should try not to use a broadside coupled stripline design. This structure is susceptible to differential noise coupled in the reference plane. In addition, balanced manufacturing of PCBs is required, which is difficult to control. In general, it is relatively easy to control the line spacing on the same layer.

Decoupling and bypass capacitors

  Another important aspect to determine whether the actual PCB performance meets expectations needs to be controlled by adding decoupling and bypass capacitors. Adding decoupling capacitors helps reduce the inductance between the PCB's power supply and the ground plane, and helps control the impedance of signals and ICs everywhere on the PCB. The bypass capacitor helps to provide a clean power supply for the FPGA (providing a charge bank). The traditional rule is that decoupling capacitors should be placed wherever PCB wiring is convenient, and the number of FPGA power pins determines the number of decoupling capacitors. However, the ultra-high switching speed of FPGA completely broke this stereotype.

In a typical FPGA board design, the capacitor closest to the power supply provides frequency compensation for load current changes. In order to provide low-frequency filtering and prevent the supply voltage from dropping, large decoupling capacitors are used. The voltage drop is due to a delay in the response of the voltage regulator when the design circuit starts. Such large capacitors are usually electrolytic capacitors with good low-frequency response, and their frequency response ranges from DC to several hundred kHz.

　Each FPGA output change requires charging and discharging the signal line, which requires energy. The function of the bypass capacitor is to provide local energy storage in a wide frequency range. In addition, a small capacitor with a small series inductance is needed to provide high-speed current for high-frequency transients. The large capacitor with slow response continues to provide current after the energy of the high-frequency capacitor is consumed.

　A large number of current transients on the power bus increase the complexity of FPGA design. This current transient is usually related to SSO/SSN. Inserting a capacitor with very small inductance will provide local high-frequency energy, which can be used to eliminate switching current noise on the power bus. The decoupling capacitor that prevents high-frequency current from entering the device power supply must be very close to the FPGA (less than 1cm). Sometimes many small capacitors are connected in parallel as the local energy storage of the device, and respond quickly to changes in current demand.

　In general, the wiring of the decoupling capacitor should be absolutely short, including the vertical distance in the via. Even a slight increase will increase the inductance of the wire, thereby reducing the effect of decoupling.

Other technologies

　As the signal speed increases, it becomes increasingly difficult to easily transmit data on the circuit board. Some other techniques can be used to further improve the performance of the PCB.

　The first and most obvious method is simple device layout. It’s common sense to design the shortest and most direct path for the most critical connections, but don’t underestimate this. Since the simplest strategy can get the best results, why bother to adjust the signal on the board?

　Almost the same simple method is to consider the width of the signal line. When the data rate is as high as 622MHz or higher, the skin effect of signal conduction becomes more prominent. When the distance is long, very thin traces on the PCB (such as 4 or 5 mils) will form a great attenuation of the signal, just like a low-pass filter with no designed attenuation, its attenuation varies with The frequency increases and increases. The longer the backplane, the higher the frequency, and the wider the width of the signal line. For backplane traces longer than 20 inches, the line width should reach 10 or 12 mils.

　Usually, the most critical signal on the board is the clock signal. When the clock line is too long or poorly designed, it will amplify jitter and offset downstream, especially when the speed increases. Should avoid using multiple layers to transmit clocks, and do not have vias on the clock line, because vias will increase impedance changes and reflections. If you must use the inner layer to lay the clock, then the upper and lower layers should use the ground plane to reduce the delay. When the design uses FPGAPLL, noise on the power plane will increase PLL jitter. If this is critical, a "power island" can be created for the PLL. This island can use a thicker etch in the metal plane to isolate the PLL analog power supply from the digital power supply.

　For signals with a rate exceeding 2Gbps, a more costly solution must be considered. At such a high frequency, the thickness of the backplane and the via design have a great influence on the integrity of the signal. The effect is better when the thickness of the backplane does not exceed 0.200 inches. When there is a high-speed signal on the PCB, the number of layers should be as few as possible, so that the number of vias can be limited. In thick boards, the via holes connecting the signal layer are longer, which will form the branch of the transmission line on the signal path. Using buried holes can solve this problem, but the manufacturing cost is high. Another option is to use low-loss dielectric materials, such as Rogers 4350, GETEK or ARLON. Compared with FR4 materials, the cost of these materials may be nearly doubled, but sometimes this is the only option.

　There are other design techniques for FPGAs, which can provide some options for I/O locations. In critical high-speed SERDES designs, SERDES I/O can be isolated by retaining (but not using) adjacent I/O pins. For example, with respect to SERDESRx and Tx, VCCRX# and VCCTX# and ball position, 3x3 or 5x5 BGA ball area can be reserved. Or if possible, you can keep the entire I/O group close to the SERDES. If there are no I/O restrictions in the design, these technologies can bring benefits without increasing costs.

　Finally, and one of the best methods is to refer to the reference board provided by the FPGA manufacturer. Most manufacturers will provide the source layout information of the reference board, although special applications may be required due to private information issues. These boards usually contain standard high-speed I/O interfaces because FPGA manufacturers need to use these interfaces when characterizing and certifying their devices. Keep in mind, however, that these circuit boards are usually designed for multiple purposes and may not exactly match specific design requirements. Even so, they can still be used as a starting point for creating solutions.

Summary of this article

　Of course, this article only talks about some basic concepts. Any of the topics covered here can be discussed in the length of the entire book. The key is to figure out what the goal is before investing a lot of time and energy in PCB layout design. Once the layout design is completed, redesigning will consume a lot of time and money, even with slight adjustments to the width of the trace. Can not rely on PCB layout engineers to make a design that can meet actual needs. The schematic designer must always provide guidance, make smart choices, and take responsibility for the success of the solution.